Fast convergent pipelined adaptive decision feedback equalizer using post-cursor processing filter

ABSTRACT

A fast convergent pipeline adaptive decision feedback equalizer using a post-cursor processing filter is disclosed, which includes a feed-forward equalizer, a post-cursor processing filter, an adder, a slicer, a register, a pipelined feedback equalizer, a subtractor and a updating device. The pipelined feedback equalizer has a delay device coupled to the register for delaying its output signal, and a feedback equalizer coupled to the delay device for eliminating the post-cursor of the output signal. By using the post-cursor processing filter (PCF), it increases the operating clock rate with arbitrary speedup factor, and improves the convergence rate of the overall system.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the technical field of adaptivedecision feedback equalizer (ADFE) and, more particularly, to a fastconvergent pipelined adaptive decision feedback equalizer (PADFE) usingpost-cursor processing filter (PCF), which is capable of eliminating theinter-symbol interference (ISI) in input samples.

2. Description of Related Art

Conventionally, the adaptive decision feedback equalizer (ADFE) usingLeast Mean-Squared (LMS) algorithm is one of the key technique in manymagnetic storage and digital communication applications. FIG. 1 shows ablock diagram of a serial adaptive decision feedback equalizer 100(ADFE). As shown, in the serial ADFE 100, a feed-forward equalizer (FFE)110 is provided for receiving the input samples x(n) and eliminatingpre-cursor of the input samples x(n). An adder 150 adds the outputsignal of the FFE 110 and a feedback signal to produce anpre-quantization signal. A slicer 130 quantizes the pre-quantizationsignal and produces a white quantized signal. A register 140 is coupledto the slicer 130 for holding the white quantized signal. A feedbackequalizer (FBE) 120 is provided for eliminating the post-cursor of thewhite quantized signal and producing the feedback signal. A subtractor160 subtracts the pre-quantization signal from the quantized signal toproduce a cost signal. An updating device 170 updates coefficients ofthe FFE 110 and FBE 120 based on the cost signal.

The updating mechanism of the serial ADFE 100 is based on the least meansquare (LMS) error algorithm. The corresponding equations of theLMS-based serial ADFE 100 can be described as follows:

{tilde over (α)}(n)=α_(F)(n)+α_(B)(n),  (1a)

X(n)=[x(n) . . . x(n−N _(f))],  (1b)

Y(n)=[{circumflex over (α)}(n−1),{circumflex over (α)}(n−2), . . .{circumflex over (α)}(n−N _(b))],  (1c)

α_(F)(n)=C ^(T)(n−1)X(n),  (1d)

α_(B)(n)=D ^(T)(n−1)Y(n),  (1e)

{circumflex over (α)}(n)=Q[{circumflex over (α)}(n)],  (1f)

e(n)={circumflex over (α)}(n)−{circumflex over (α)}(n),  (1g)

C(n)=C(n−1)+μe(n)X(n),  (1h)

D(n)=D(n−1)+μe(n)Y(n),  (1i)

where

α_(F)(n) is the output of FFE,

α_(B)(n) is the output of FBE,

C(n) is the vector of FFE coefficients,

D(n) is the vector of FBE coefficients,

X(n) is the vector of received samples,

Y(n) is the vector of detected symbols,

ã (n) is the input of the slicer Q(•),

â (n) is the output of the slicer Q(•).

However, fine-grain pipelining of the serial ADFE 100 is known to be adifficult problem for high-speed applications and operating clock rateof the serial ADFE 100 is limited by a decision feedback loop (DFL) asshown in FIG. 1.

FIG. 2 shows a block diagram of a pipelined adaptive decision feedbackequalizer 200 (PIPEADFE) for increasing the operating clock rate of theADFE 100. To achieve the pipeline, a delay device 210 is introduced inthe decision feedback loop. The delay device 210 is coupled between theregister 140 and the feedback equalizer 120 for delaying the whitequantized signal and increasing the number of pipeline stages for thefeedback equalizer 120.

The equations for describing the pipeline adaptive decision feedbackequalizer 200 (PIPEADFE) are summarized below:

{tilde over (α)}(n)=α_(F)(n)+α_(B)(n),  (2a)

X(n)=[x(n),x(n−1), . . . x(n−N _(f)+1)],  (2b)

Y(n)=[{circumflex over (α)}(n−1−D ₁),{circumflex over (α)}(n−1−D ₁), . .. {circumflex over (α)}(n−D ₁ −N _(b))],  (2c)

α_(F)(n)=C ^(T)(n−D ₄)X(n),  (2d)

α_(B)(n)=D ^(T)(n−D ₄)Y(n),  (2e)

{circumflex over (α)}(n)=Q[{tilde over (α)}(n)],  (2f)

e(n)={circumflex over (α)}(n)−{tilde over (α)}(n),  (2g)

$\begin{matrix}{{{C(n)} = {{C\left( {n - D_{4}} \right)} + {\mu {\sum\limits_{i = 0}^{{LA} - 1}{{e\left( {n - D_{2} - i} \right)}{X\left( {n - D_{2} - i} \right)}}}}}},} & \left( {2h} \right) \\{{{D(n)} = {{D\left( {n - D_{4}} \right)} + {\mu {\sum\limits_{i = 0}^{{LA} - 1}{{e\left( {n - D_{3} - i} \right)}{Y\left( {n - D_{3} - i} \right)}}}}}},} & \left( {2i} \right)\end{matrix}$

The pipelined adaptive decision feedback equalizer (PIPEADFE) 200maintains the functionality in the statistical behavior instead ofinput-output behavior by using the relaxed look-ahead technique.However, it suffers from some performance degradation such as output SNRand convergence rate. Although, the operating clock rate of the PIPEADFE200 is large than the ADFE 100. But the convergence rate of PIPEADFE 200is quite slower than the ADFE 100. Therefore, there is a need to have anovel design of pipeline adaptive decision feedback equalizer that canmitigate and/or obviate the aforementioned problems.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a fast convergentpipelined adaptive decision feedback equalizer using a post-cursorprocessing filter for eliminating the inter-symbol interference (ISI) ininput samples, so as to increase operating clock rate and convergencerate of overall system.

To achieve the aforementioned object, there is provided a fastconvergent pipelined adaptive decision feedback equalizer using apost-cursor processing filter, which comprises a feed-forward equalizer,a post-cursor processing filter, an adder, a slicer, a register, apipelined feedback equalizer, a subtractor and an updating device. Thefeed-forward equalizer is provided for receiving input samples andeliminating pre-cursor of the input samples. The post-cursor processingfilter is coupled to the feed-forward equalizer for producing an outputsignal. The adder is provided for adding the output signal of thepost-cursor processing filter and a feedback signal to produce anpre-quantization signal. The slicer is coupled to the adder forquantizing the pre-quantization signal and producing a white quantizedsignal. The register is coupled to the slicer for holding the whitequantized signal. The pipelined feedback equalizer has plurality ofpipeline stages and is coupled to the register for eliminating thepost-cursor of the white quantized signal and producing the feedbacksignal. The subtractor is provided for subtracting the pre-quantizationsignal from the quantized signal to produce a cost signal. The updatingdevice is provided for updating coefficients of the feed-forwardequalizer and pipelined feedback equalizer based on the cost signal andupdating coefficients of the post-cursor processing filter based on thecost signal and the white quantized signal.

Other objects, advantages, and novel features of the invention willbecome more apparent from the following detailed description when takenin conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of a conventional serial adaptive decisionfeedback equalizer (ADFE);

FIG. 2 shows a block diagram of a conventional pipeline adaptivedecision feedback equalizer (PIPEADFE);

FIG. 3 shows a block diagram of a fast convergent pipelined adaptivedecision feedback equalizer using a post-cursor processing filter(PCFADFE) in accordance with the present invention;

FIG. 4 shows an embodied circuit with a speedup factor of three inaccordance with the present invention;

FIGS. 5(a)-(c) show parameter tables for simulation of channel I, II,and III, respectively;

FIGS. 6(a)-(c) show simulation results according to the parameters inFIG. 5, respectively;

FIG. 7 shows the output SNR of PIPEADFE and PCFADFE vs. speedup factor;and

FIG. 8 shows the hardware complexity of PIPEADFE and PCFADFE in speedupfactor being equal to 2 and N.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

With reference to FIG. 3, there is shown a functional block diagram of afast convergent pipelined adaptive decision feedback equalizer usingpost-cursor processing filter 300 (PCFADFE) according to the presentinvention, which includes a feed-forward equalizer 310, a post-cursorprocessing filter 320, an adder 330, a slicer 340, a register 350, apipelined feedback equalizer 360, a subtractor 370, and an updatingdevice 380. The feed-forward equalizer 310 receives the input samplesx(n) and eliminates pre-cursor of the input samples x(n). Thepost-cursor processing filter 320 is coupled to the feed-forwardequalizer 310 and produces an output signal. The adder 330 adds theoutput signal of the post-cursor processing filter 320 and a feedbacksignal to produces a pre-quantization signal. The slicer 340 is coupledto the adder 330 for quantizing the pre-quantization signal andproducing a white quantized signal. The register 350 is coupled to theslicer 340 for holding the white quantized signal. The pipelinedfeedback equalizer 360 includes a delay device 361 coupled to theregister 350 for delaying the white quantized signal, and a feedbackequalizer 362 coupled to the delay device 361 for eliminating thepost-cursor of the white quantized signal and producing the feedbacksignal. The subtractor 370 subtracts the pre-quantization signal fromthe quantized signal to produce a cost signal. The updating device 380updates the coefficients of the feed-forward equalizer 310 and feedbackequalizer 362 based on the cost signal and updates coefficients of thepost-cursor processing filter 320 based on the cost signal and the whitequantized signal.

Because the difference between the input and output of the slicer 340 issmall, the behavior of DFE is close to an IIR filter with the transferfunction as follows: $\begin{matrix}{{P(z)} = {\frac{N(z)}{D(z)}.}} & (3)\end{matrix}$

where N(z) is a transfer function of the feed-forward equalizer (FFE)310, D(z) is a transfer function of the feedback equalizer (FBE) 362.

The decision feedback loop (DFL) can be pipelined by inserting apolynomial${{Q(z)} = {\sum\limits_{i = 0}^{D_{1}}{q_{i}z^{- i}}}},{q_{0} = 1}$

to the numerator and denominator of equation (3). With the same numberof poles and zeros being inserted in the numerator and denominator ofequation (3), it is able to de-correlate the dependence of the outputand the first D₁ ISI terms. The corresponding equation is given below:$\begin{matrix}{{{P(z)} = {\frac{N(z)}{D(z)} = {\frac{{Q(z)}{N(z)}}{{Q(z)}{D(z)}} = \frac{{Q(z)}{N(z)}}{1 - {z^{- {({D_{1} + 1})}}{R(z)}}}}}},} & (4)\end{matrix}$

where ${R(z)} = {\sum\limits_{i = 0}^{k}{r_{i}{z^{- i}.}}}$

With the extra delay device 361 that includes D₁ delay elements, thefeedback equalizer 362 on the decision feedback loop (DFL) can bepipelined with D₁ pipeline stages. Then, a highest operating clock rateof the pipeline adaptive decision feedback equalizer 300 can beincreased to a factor of (D₁+1).

The coefficients of the feed-forward equalizer (FFE) 310 and feedbackequalizer (FBE) 362 are dynamically updated based on minimizing a firstcost function: ∥e(n)∥², where e(n) is the cost signal. That is, theupdating device 380 dynamically adjusts the coefficients of thefeed-forward equalizer (FFE) 310 and feedback equalizer (FBE) 362 basedon minimizing the first cost function: ∥e(n)∥². By applying thestochastic gradient-based algorithm and technique of Sum-Relaxatio, thecoefficients of the feed-forward equalizer (FFE) 310 and feedbackequalizer (FBE) 362 can be respectively expressed as follows:$\begin{matrix}{{{C(n)} = {{C\left( {n - D_{4}} \right)} + {\mu {\sum\limits_{i = 0}^{{LA} - 1}{{e\left( {n - D_{2} - i} \right)}{X\left( {n - D_{2} - i} \right)}}}}}},} & (5)\end{matrix}$

$\begin{matrix}{{{D(n)} = {{D\left( {n - D_{4}} \right)} + {\mu {\sum\limits_{i = 0}^{{LA} - 1}{{e\left( {n - D_{3} - i} \right)}{Y\left( {n - D_{3} - i} \right)}}}}}},} & (6)\end{matrix}$

According to the “Principle of Orthogonality”, the coefficients of thepost-cursor processing filter (PCF) 320 are updated based on minimizinga second cost function: $\begin{matrix}{{\underset{P_{1}}{Min}\left\{ {E^{2}\left\{ {{e(n)}{a\left( {n - 1} \right)}} \right\}} \right\}},{\underset{P_{2}}{Min}\left\{ {E^{2}\left\{ {{e(n)}{a\left( {n - 2} \right)}} \right\}} \right\}},\ldots \quad,} \\{{\underset{P_{D_{1}}}{Min}\left\{ {E^{2}\left\{ {{e(n)}{a\left( {n - D_{1}} \right)}} \right\}} \right\}},}\end{matrix}$

where e(n) is the cost signal, a(n) is the white quantized signal, andP(n)={P1,P2, . . . , PD1} represents the coefficients of the post-cursorprocessing filter (PCF) 320. The coefficients of the post-cursorprocessing filter (PCF) 320 are represented as follows: $\begin{matrix}{{{P(n)} = {{P\left( {n - D_{4}} \right)} + {\mu {\sum\limits_{i = 0}^{{LA} - 1}{{e\left( {n - D_{5} - i} \right)}{Z\left( {n - D_{5} - i} \right)}}}}}},} & (7)\end{matrix}$

where Z(n)=[a(n−1) . . . a(n−D₁)].

FIG. 4 shows an embodied circuit of present invention with a speedupfactor of three (D₁=2). That is, the iteration bound of serial ADFE asshown in FIG. 1 is three times than the PCFADFE 400. This implies thatthere is two extra delay elements (D₁=2) inserted into the delayfeedback loop (DFL). It is assumed that the transmitted data, w(n)(change a(n) to w(n)), is an independent sequence, and input data ofreceiver is x(n). The input data x(n) can be expressed as follows:

x(n)=h ⁻¹ w(n+1)+h ₀ w(n)+h ₁ w(n−1)+h ₂ w(n−2)+v(n),  (8)

where h⁻¹,h₀,h₁,h₂, are channel impulse response, v(n) is the additivewhite Gaussian noise (AWGN). The number of taps in FFE 310 and FBE 362are three and two, respectively. Since D₁=2, the number of taps in thePCF is three (D₁+1) in this embodiment. The i-th coefficients of FFE310, PCF 320 and FBE 362 at time instance n are denoted as c_(i), p_(i),and b_(i), respectively. With above notations, an estimation error orcost function e(n) can be expressed as: $\begin{matrix}\begin{matrix}{{e(n)} = \quad {{w(n)} - {F(n)} - {P(n)}}} \\{= \quad {{w(n)} - {F(n)} - {p_{1}{F\left( {n - 1} \right)}} - {p_{2}{F\left( {n - 2} \right)}} - {B(n)}}}\end{matrix} & \left( {9a} \right) \\{{{F(n)} = {\sum\limits_{i = 0}^{2}{c_{i}{x\left( {n + i} \right)}}}},} & \left( {9b} \right) \\{{{B(n)} = {\sum\limits_{i = 1}^{2}{b_{i}{w\left( {n - 2 - i} \right)}}}},} & \left( {9c} \right)\end{matrix}$

where F(n) is the output of FFE 310, and B(n) is the output of FBE 362.P(n) denotes the total effect of PCF 320 and FBE 310 at time instance n,and can be written as: $\begin{matrix}\begin{matrix}{{P(n)} = \quad {{p_{1}{F\left( {n - 1} \right)}} + {p_{2}{F\left( {n - 2} \right)}} + {B(n)}}} \\{{= \quad {{\sum\limits_{i = {- 2}}^{4}{s_{i}{w\left( {n - i} \right)}}} + {\eta (n)}}},}\end{matrix} & (10)\end{matrix}$

where η(n) is a noise component.

In the serial ADFE 100 as shown in FIG. 1, the objective of the FFE 110is to minimize E{e²(n)}. In the FFE 310 of the PCFADFE 400, it intendsto minimize e²(n) instead of E{e²(n)}. In order to apply stochasticgradient-based algorithm, it must find the gradient of this costfunction e(n). Moreover, the total effect of PCF 320 and FBE 362 in timeinstance n can be considered as a constant. Hence, the gradientscorresponding to c_(i) are listed as follows: $\begin{matrix}{{\frac{\partial{e(n)}^{2}}{\partial c_{0}} = {{- 2}{e(n)}{x(n)}}},} & \left( {11a} \right) \\{{\frac{\partial{e(n)}^{2}}{\partial c_{1}} = {{- 2}{e(n)}{x\left( {n + 1} \right)}}},} & \left( {11b} \right) \\{{\frac{\partial{e(n)}^{2}}{\partial c_{2}} = {{- 2}{e(n)}{x\left( {n + 2} \right)}}},} & \left( {11c} \right)\end{matrix}$

The results as listed above are similar to those of the serial ADFE 100.Hence, the main functionality of the FFE 310 in PCFADFE 400 is to cancelthe precursor ISI terms. In present embodiment, it employs a dedicatedPCF 320 to de-correlate the correlation between the first twopost-cursor ISI terms and ADFE output. The remaining ISI terms will becanceled by FFE 310 and FBE 362, respectively.

Considering the PCF 320 and FBE 362, the output of FFE 310 at timeinstance n can be written as $\begin{matrix}{{F(n)} = {{\sum\limits_{i = 0}^{2}{c_{i}{x\left( {n + i} \right)}}} = {\sum\limits_{i = {- 3}}^{2}{r_{i}{{w\left( {n - i} \right)}.}}}}} & (12)\end{matrix}$

F(n) represents sum of the residual ISI terms that cannot be canceled byFFE 310 at time instance n. It is noted that, in the serial ADFE 100 asshown in FIG. 1, the prediction error must be orthogonal to theobservations in the steady state, which is known as “OrthogonalPrinciple” in the literature of adaptive signal processing. It impliesthat minimizing the estimation error is equivalent to de-correlate thecorrelation between observations and filter output. Therefore, theobjective of the PCF 320 is to minimize the following two expectationterms: $\begin{matrix}{{\underset{p_{1}}{Min}\left\{ {E^{2}\left\{ {{e(n)}{w\left( {n - 1} \right)}} \right\}} \right\}},} & \left( {13a} \right) \\{{\underset{p_{2}}{Min}\left\{ {E^{2}\left\{ {{e(n)}{w\left( {n - 2} \right)}} \right\}} \right\}},} & \left( {13b} \right)\end{matrix}$

where p₁,p₂ are the coefficients of the 2-tap PCF 320. Next, thegradients corresponding to these cost functions are listed as follows:$\begin{matrix}\begin{matrix}{\frac{{\partial E^{2}}\left\{ {{w\left( {n - 1} \right)}{e(n)}} \right\}}{\partial p_{1}} = \quad {2{r_{0}\left( {r_{1} + {p_{1}r_{0}} + {p_{2}r_{- 1}}} \right)}E^{2}\left\{ {w^{2}\left( {n - 1} \right)} \right\}}} \\{{= \quad {{- 2}r_{0}E\left\{ {{e(n)}{w\left( {n - 1} \right)}} \right\} E\left\{ {w^{2}\left( {n - 1} \right)} \right\}}},}\end{matrix} & \left( {14a} \right)\end{matrix}$

$\begin{matrix}\begin{matrix}{\frac{{\partial E^{2}}\left\{ {{w\left( {n - 2} \right)}{e(n)}} \right\}}{\partial p_{2}} = \quad {2{r_{0}\left( {r_{2} + {p_{1}r_{1}} + {p_{2}r_{0}}} \right)}E^{2}\left\{ {w^{2}\left( {n - 2} \right)} \right\}}} \\{= \quad {{- 2}r_{0}E\left\{ {{e(n)}{w\left( {n - 2} \right)}} \right\} E{\left\{ {w^{2}\left( {n - 2} \right)} \right\}.}}}\end{matrix} & \left( {14b} \right)\end{matrix}$

Because the direction of gradient is more important than the magnitudeof gradient in stochastic gradient-based algorithm, it can approximatethe gradient of (15) as follows: $\begin{matrix}{{\frac{{\partial E}\left\{ {{w^{2}\left( {n - 1} \right)}{e^{2}(n)}} \right\}}{\partial p_{1}} \cong {{- 2}E\left\{ {{e(n)}{w\left( {n - 1} \right)}} \right\}}},} & \left( {15a} \right) \\{\frac{{\partial E}\left\{ {{w^{2}\left( {n - 2} \right)}{e^{2}(n)}} \right\}}{\partial p_{2}} \cong {{- 2}E{\left\{ {{e(n)}{w\left( {n - 2} \right)}} \right\}.}}} & \left( {15b} \right)\end{matrix}$

In FBE 362, it intends to minimize the same cost function of FFE 310.The gradients corresponding to FBE 362 are: $\begin{matrix}{{\frac{{\partial E}\left\{ {e^{2}(n)} \right\}}{\partial b_{1}} = {{- 2}E\left\{ {{e(n)}{w\left( {n - 3} \right)}} \right\}}},} & \left( {16a} \right) \\{\frac{{\partial E}\left\{ {e^{2}(n)} \right\}}{\partial b_{2}} = {{- 2}E{\left\{ {{e(n)}{w\left( {n - 4} \right)}} \right\}.}}} & \left( {16b} \right)\end{matrix}$

The equations derived for this embodiment can be generalized to thegeneral case with arbitrary taps and arbitrary speedup factor. Finally,by combining with Delayed-LMS, Sum Relaxed Look-ahead and generalizedcases of (11a), (15a), (16a), the equations to describe the PCFADFE 400embodiment can be written as $\begin{matrix}{{{X(n)} = \left\lbrack {{x(n)}\quad \ldots \quad \ldots \quad {x\left( {n - N_{f} + 1} \right)}} \right\rbrack},} & \left( {17a} \right) \\{{{Y(n)} = \left\lbrack {{\hat{a}\left( {n - D_{1} - 1} \right)}\quad \ldots \quad {\hat{a}\left( {n - D_{1} - N_{b}} \right)}} \right\rbrack}\quad} & \left( {17b} \right) \\{{{{Z(n)} = \left\lbrack {{\hat{a}\left( {n - 1} \right)}\quad \ldots \quad \ldots \quad {\hat{a}\left( {n - D_{1}} \right)}} \right\rbrack},}\quad} & \left( {17c} \right) \\{{{P(n)} = \left\lbrack {{p_{1}(n)}\quad \ldots \quad \ldots \quad {p_{D_{1}}(n)}} \right\rbrack},} & \left( {17d} \right) \\{{{F(n)} = {{C^{T}\left( {n - D_{4}} \right)}{X(n)}}},} & \left( {17e} \right) \\{{{B(n)} = {{D^{T}\left( {n - D_{4}} \right)}{Y(n)}}},} & \left( {17f} \right) \\{{{\overset{\sim}{a}(n)} = {{\sum\limits_{i = 0}^{D_{1}}{{p_{j}\left( {n - D_{4}} \right)}{F\left( {n - j} \right)}}} + {B(n)}}},{p_{0} = 1},} & \left( {17g} \right) \\{{{\overset{\sim}{a}(n)} = {Q\left\lbrack {\overset{\sim}{a}(n)} \right\rbrack}},} & \left( {17h} \right) \\{{{e(n)} = {{\hat{a}(n)} - {\overset{\sim}{a}(n)}}},} & \left( {17i} \right) \\{{{C(n)} = {{C\left( {n - D_{4}} \right)} + {\mu {\sum\limits_{i = 0}^{{LA} - 1}{{e\left( {n - D_{2} - i} \right)}{X\left( {n - D_{2} - i} \right)}}}}}},} & \left( {17j} \right) \\{{{D(n)} = {{D\left( {n - D_{4}} \right)} + {\mu {\sum\limits_{i = 0}^{{LA} - 1}{e\left( {n - D_{3} - i} \right){Y\left( {n - D_{3} - i} \right)}}}}}},} & \left( {17k} \right) \\{{{P(n)} = {{P\left( {n - D_{4}} \right)} + {\mu {\sum\limits_{i = 0}^{{LA} - 1}{e\left( {n - D_{5} - i} \right){Z\left( {n - D_{5} - i} \right)}}}}}},} & \left( {17l} \right)\end{matrix}$

where p_(j) denotes the j-th coefficient of the PCF 320. Thecorresponding hardware architecture of PCFADFE 400 is shown in FIG. 4,where D_(m) 390 are the dummy delays in order to pipeline feed-forwardpart of PCFADFE 400.

To verify the performance of present invention, t a simulation isperformed on the serial ADFE 100, PIPEADFE 200 and PCFADFE 400 accordingto the present invention. In the simulation, three types of channelmodels are employed. In the first channel model (Channel I), it assumesthat the channel impulse response, h=[0.2 0.6 1.0 −1.0 −0.6 −0.2], isobtained from a Lorentian pulse mode. The second channel impulseresponse (Channel II), h=[0.3365 1 0.3365], is obtained from typicalchannel models. The third channel impulse response (Channel III) is thetypical channel impulse response of UTP-CAT-5, which is often employedin fast Ethernet applications. The transmitted data w(n) for all channelmodels is a PAM5 random sequence, w(n) ∈{−1, −0.5, 0, 0.5, 1}.

In the first simulation, it evaluate the convergence performance of bothequalizers with input SNR=30 dB. The parameter settings of serial ADFE100, PIPEADFE 200 and PCFADFE 400 according to the present invention forthese three channel models are listed in FIG. 5. With the parameterssetting, the learning curves of PIPEADFE 200 and PCFADFE 400 for thesechannel models are shown in FIG. 6. Based on the results shown in FIG.6, it shows that the convergence rate of PCFADFE 300 is faster than thatof PIPEADFE 200. That is, the convergence performance is significantlyimproved by introducing the post-cursor processing filter (PCF) 320. Itis known that the convergence rate of the conventional LMS-based serialADFE 100 depends on the step size and the channel spectralcharacteristics, which relate to the eigenvalue (λ_(n)) of the receivedsignal autocorrelation matrix. If the channel amplitude and phasedistortions are small, the eigenvalue ratio (Max(λ_(n))/Min(λ_(n))) isclose to one and, the serial ADFE 100 converges to its optimal tapcoefficients relatively fast. On the contrary, if the channel exhibitspoor spectral characteristics, such as relatively large attenuation in apart of its spectrum, the eigenvalue ratio will be larger than one (i.e.Max(λ_(n))/Min(λ_(n))>>1). Thus, the convergence rate of LMS-basedserial ADFE will be slow. By using the post-cursor processing filter(PCF), the decisions or the training sequences can be applied to theupdating mechanism. By applying the train sequences or decisions intothe updating mechanisms, the eigenvalue spread of input signal should bereduced. Thus, the convergence rate of PCFADFE can be faster than thePIPEADFE 200.

As shown in FIG. 6, it is known that the PIPEADFE 200 and the PCFADFE400 suffer from output SNR degradation in comparison with the serialADFE 100. FIG. 7 shows how the output SNR of PIPEADFE 200 and PCFADFE400 is degraded as the speedup factor is increased. The channel I isused and the parameters of PIPEADFE 200 and PCFADFE 400 are the same asshown in FIG. 5, except that D₁=speedup−1 and input SNR=28.451. Thenumber of transmitted data samples in both PIPEADFE 200 and PCFADFE 400is 10000. As shown, the output SNR and speedup factor are the x and ycoordinates respectively. It can be seen that both PIPEADFE 200 andPCFADFE 400 have an output SNR loss of about 0.5 dB per unit increase inthe speedup factor. Because the output SNR depends on the number of tapsin FFE and PCF, it can choose the number of taps in FFE and PCF in orderto make both architectures achieve the same output SNR, wherein thenumber of taps of FFE in PIPEADFE 200 is N_(f)+D₁, the number of taps ofFFE in PCFADFE 400 is N_(f), and the number of taps of PCF in PCFADFE400 is D₁. Moreover, the number of taps in FBE is fixed on N_(b) (Notethat N_(f) and N_(b) are the number of taps of FFE and FBE in serialADFE 100). The speedup factor versus hardware complexity is shown inFIG. 8. It can be seen that the hardware complexities of PIPEADFE 200and PCFADFE 400 are the same. Nevertheless, the convergent rate ofPCFADFE 300 is much faster than that of the PIPEADFE 200.

In view of the foregoing, it is known that the present inventionutilizes the post-cursor processing filter (PCF) to not only increasethe operating clock rate with arbitrary speedup factor but alsodramatically improve the convergence rate of the overall system.Furthermore, the hardware overhead of the present invention is the sameas the pipeline ADFE 200 (PIPEADFE).

Although the present invention has been explained in relation to itspreferred embodiment, it is to be understood that many other possiblemodifications and variations can be made without departing from thespirit and scope of the invention as hereinafter claimed.

What is claimed is:
 1. A fast convergent pipelined adaptive decisionfeedback equalizer using a post-cursor processing filter, comprising: afeed-forward equalizer for receiving input samples and eliminatingpre-cursor of the input samples; a post-cursor processing filter coupledto the feed-forward equalizer and producing an output signal; an adderfor adding the output signal of the post-cursor processing filter and afeedback signal to producing an pre-quantization signal; a slicercoupled to the adder for quantizing the pre-quantization signal andproducing a white quantized signal; a register coupled to the slicer forholding the white quantized signal; a pipelined feedback equalizerhaving plurality of pipeline stages and coupling to the register foreliminating the post-cursor of the white quantized signal and producingthe feedback signal; a subtractor for subtracting the pre-quantizationsignal from the quantized signal to produce a cost signal; and anupdating device for updating coefficients of the feed-forward equalizerand pipelined feedback equalizer based on the cost signal and updatingcoefficients of the post-cursor processing filter based on the costsignal and the white quantized signal.
 2. The fast convergent pipelinedadaptive decision feedback equalizer as claimed in claim 1, wherein thepipelined feedback equalizer comprises a delay device coupled to theregister for delaying the white quantized signal, and a feedbackequalizer coupled to the delay device for eliminating the post-cursor ofthe white quantized signal and producing the feedback signal.
 3. Thefast convergent pipelined adaptive decision feedback equalizer asclaimed in claim 2, wherein the post-cursor processing filter is formedby inserting the same poles and zeros pairs:${{P(z)} = {\frac{N(z)}{D(z)} = {\frac{{Q(z)}{N(z)}}{{Q(z)}{D(z)}} = \frac{{Q(z)}{N(z)}}{1 - {z^{- {({D_{1} + 1})}}{R(z)}}}}}},$

where N(z) is a transfer function of the feed-forward equalizer, D(z) isa transfer function of the feedback equalizer,${Q(z)} = {\sum\limits_{i = 0}^{D_{1}}{q_{i}z^{- i}}}$

is a transfer function of the post-cursor processing filter, parameterD₁ is the number of delay elements in the delay device.
 4. The fastconvergent pipelined adaptive decision feedback equalizer as claimed inclaim 3, wherein a highest operating clock rate of the pipeline adaptivedecision feedback equalizer can be increased to a factor of (D₁+1). 5.The fast convergent pipelined adaptive decision feedback equalizer asclaimed in claim 1, wherein the coefficients of the feed-forwardequalizer and feedback equalizer are updated based on minimizing a firstcost function: ∥e(n)∥², where e(n) is the cost signal.
 6. The fastconvergent pipelined adaptive decision feedback equalizer as claimed inclaim 1, wherein the coefficients of the post-cursor processing filterare updated based on minimizing a second cost function: $\begin{matrix}{{\underset{P_{1}}{Min}\left\{ {E^{2}\left\{ {{e(n)}{a\left( {n - 1} \right)}} \right\}} \right\}},{\underset{P_{2}}{Min}\left\{ {E^{2}\left\{ {{e(n)}{a\left( {n - 2} \right)}} \right\}} \right\}},\ldots \quad,} \\{\underset{P_{D_{1}}}{Min}\left\{ {E^{2}\left\{ {{e(n)}{a\left( {n - D_{1}} \right)}} \right\}} \right\}}\end{matrix}$

where e(n) is the cost signal, α(n) is the white quantized signal, andP(n)={P1,P2, . . . , PD1} represents the coefficients of the post-cursorprocessing filter.
 7. The fast convergent pipelined adaptive decisionfeedback equalizer as claimed in claim 5, wherein the coefficients ofthe post-cursor processing filter are updated based on minimizing asecond cost function: $\begin{matrix}{{\underset{P_{1}}{Min}\left\{ {E^{2}\left\{ {{e(n)}{a\left( {n - 1} \right)}} \right\}} \right\}},{\underset{P_{2}}{Min}\left\{ {E^{2}\left\{ {{e(n)}{a\left( {n - 2} \right)}} \right\}} \right\}},\ldots \quad,} \\{\underset{P_{D_{1}}}{Min}\left\{ {E^{2}\left\{ {{e(n)}{a\left( {n - D_{1}} \right)}} \right\}} \right\}}\end{matrix}$

where e(n) is the cost signal, α(n) is the white quantized signal, andP(n)={P1,P2, . . . , PD1} represents the coefficients of the post-cursorprocessing filter.
 8. The fast convergent pipelined adaptive decisionfeedback equalizer as claimed in claim 7, wherein the coefficients ofthe post-cursor processing filter are:${{P(n)} = {{P\left( {n - D_{4}} \right)} + {\mu {\sum\limits_{i = 0}^{{LA} - 1}{{e\left( {n - D_{5} - i} \right)}{Z\left( {n - D_{5} - i} \right)}}}}}},$

where Z(n)=[a(n−1) . . . a(n−D₁)].